In system chips, usually digital and analog signals are processed. Signals in the system should be converted from one domain to the other. Analog to digital conversion may be necessary for complex digital processing, such as by a digital signal processor (DSP). Such conversion may be performed by Analog-to-Digital Converters (ADC).
A Successive Approximation Register (SAR) ADC converts an analog signal into a digital representation through several stages. Each stage, analog voltages are compared in order to produce a bit. In a SAR ADC, first the input voltage is sampled and held in the circuit, then a comparator compares the input voltage with the output of an internal Digital-to-Analog Converter (DAC) and sends the comparison result to a SAR. This first approximated digital code of the input signal is sent from the SAR to the DAC, which converts the value to an analog signal for supplying this signal to the comparator in order to compare this first approximation with the input signal. In “All MOS Charge Redistribution Analog-to-Digital Conversion Techniques—Part I” by Mc Creary and Gray, IEEE Journal of solid state, vol. sc-10, num. 6, December 1975, a special implementation of a SAR-ADC comprising a capacitive charge redistribution SAR-ADC is disclosed. In this implementation the DAC consists of a capacitive network and this capacitive network also acts as the sample capacitor. This kind of ADC's have a very good performance in terms of speed, power, and chip-area. Mainly, two kinds of sampling approaches are used in these circuits, a top plate sampling approach wherein the input signal is sampled at the input lines to the comparator, and a bottom plate sampling approach, wherein the input signal is sampled at the entrance of the DAC.
In a SAR ADC, the successive Approximation Register is initialized, for example with only the most significant bit set to one. This value is sent to the DAC, which converts it to its analog value (half of the reference voltage) for sending it to the comparator for comparing with the input signal. If the analog voltage exceeds the input signal, the SAR switches this bit to zero, otherwise it is left to one. In the next step, the next bit in the SAR is set to one and the same process is performed.
Very often, the DAC in the SAR ADC is implemented with an array of capacitors. In this case, if a differential structure of the array of capacitors is used, interferences in the circuit will be cancelled. This is an important advantage. Due to the small values of the capacitors in that kind of circuits, important interferences may appear.
The consequence of using a differential structure for the array of capacitors is that also a differential input signal should be sampled. However, in many applications, a single ended signal is available. One possible solution is to introduce an extra circuit before the ADC that converts the single ended signal to a differential signal. However, the new circuit will introduce additional area, additional power dissipation, and time delays.